Important: Figures presented below are representative placeholders illustrating the benchmark structure. Some results are from hardware-backed experiments on real quantum devices; other categories describe projected capabilities of future embodiments that require deeper hardware access. All numbers should be independently validated. Contact us for full benchmark documentation.

Trajectory Filtering

Improvement in expectation-value estimates after applying trajectory filtering to standard quantum circuit outputs.

+15%
Expectation Value Accuracy
sample · 5-qubit GHZ · IBM hardware
+12%
Observable Fidelity
sample · random Clifford benchmark
−22%
Variance Reduction
sample · 8-qubit circuit

Blue: baseline | Cyan: with qgate trajectory filtering · placeholder visualization

Depth Scaling

How filtering performance holds as circuit depth increases.

2.3×
Effective Depth Extension
sample · comparable fidelity threshold
Stable
Scaling Behavior
sample · linear depth range tested
5–20
Depth Range (layers)
sample · characterization window

Shot Efficiency

Reduction in required shot count to achieve a target accuracy.

40%
Fewer Shots Required
sample · fixed accuracy target
1.7×
Throughput Multiplier
sample · equivalent fidelity

Noise Robustness

Performance across varying noise regimes and device calibrations.

Consistent
Cross-Device Behavior
sample · tested on multiple backends
Adaptive
Calibration Sensitivity
sample · tracks drift conditions
Graceful
High-Noise Degradation
sample · no catastrophic failure modes

Future: Control-Path Validation

Projected benchmarks for the non-public control layers. These require hardware-level telemetry access and are not yet validated on production quantum hardware.

Projected

Observable Reconstruction Gain

Expected improvement over trajectory filtering alone when calibration-driven reconstruction is applied. Requires Level-1 data access.

Pending hardware access
Projected

Runtime Control Latency Budget

Target latency envelope for telemetry-driven control decisions. Depends on FPGA integration and hardware-level data path design.

Pending hardware access
Category 5 benchmarks describe architectural targets for future embodiments. They are not claims about current production capability. Validation requires partnerships with quantum hardware vendors and FPGA control providers.

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